Համահեղինակ(ներ):

Shoukourian Samvel ; Vardanian Valery ; Zorian Yervant

Ամփոփում:

A new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms was introduced recently. These rules are represented in a form of a Fault Periodicity Table (FPT) considering both known and unknown memory faults in one table. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. In this paper, application of the proposed methodology for description of memory faults in technologies below 20nm, including 16/14nm FinFET-based memories, is shown. Specifically, it is shown that all recently discovered FinFET-specific faults successfully fit into FPT.

Հրատարակիչ:

IEEE

Նույնականացուցիչ:

oai:noad.sci.am:136123

DOI:

10.1109/EWDTS.2014.7027088

ISBN:

978-1-4799-7630-0

ORCID:

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Լեզու:

English

Հատոր:

13

URL:

Կազմակերպության անվանում:

Synopsys Armenia

Երկիր:

Ukraine

Տարի:

2014

Ժամանակահատված:

26-29 September

Գիտաժողովի անվանում:

Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)

Վայր:

Kiev