Object

Title: Fault modeling and test algorithm creation strategy for FinFET-based memories

Co-author(s) :

Tshagharyan Grigor ; Vardanian Valery ; Zorian Yervant

Abstract:

FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs.

Publisher:

IEEE

Identifier:

oai:noad.sci.am:136124

DOI:

10.1109/VTS.2014.6818747

ISBN:

978-1-4799-2611-4

ORCID:

click here to follow the link

Language:

English

Volume:

32

URL:


Affiliation:

Synopsys

Country:

USA

Year:

2014

Time period:

13-17 April

Conference title:

2014 IEEE 32nd VLSI Test Symposium (VTS)

Place:

Napa, CA

Object collections:

Last modified:

Apr 19, 2021

In our library since:

Apr 19, 2021

Number of object content hits:

11

All available object's versions:

https://noad.sci.am/publication/149624

Show description in RDF format:

RDF

Show description in OAI-PMH format:

OAI-PMH

Objects

Similar

This page uses 'cookies'. More information